The present invention relates generally to integrated circuit layout and semiconductor electronics, and more particularly to multi-level metal technology and the reduction of the probability of interlevel oxide failures through a modified bus design.
The phenomenon of field emission was discovered in the 1950""s, and extensive research by many individuals has developed the technology to the extent that its use in inexpensive, low-power, high-resolution, high-contrast, full-color flat displays appears promising. Advances in field emission device (xe2x80x9cFEDxe2x80x9d) display technology are disclosed in U.S. Pat. No. 3,755,704, xe2x80x9cField Emission Cathode Structures and Devices Utilizing Such Structures,xe2x80x9d issued Aug. 28, 1973, to C. A. Spindt et al.; U.S. Pat. No. 4,940,916, xe2x80x9cElectron Source with Micropoint Emissive Cathodes and Display Means by Cathodoluminescence Excited by Field Emission Using Said Source,xe2x80x9d issued Jul. 10, 1990 to Michel Borel et al.; U.S. Pat. No. 5,194,780, xe2x80x9cElectron Source with Microtip Emissive Cathodes,xe2x80x9d issued Mar. 16, 1993 to Robert Meyer; and U.S. Pat. No. 5,225,820, xe2x80x9cMicrotip Trichromatic Fluorescent Screen,xe2x80x9d issued Jul. 6, 1993, to Jean-Frxc3xa9dxc3xa9ric Clerc. These patents are incorporated by reference into the present application.
A FED flat panel display arrangement is disclosed in U.S. Pat. No. 4,857,799, xe2x80x9cMatrix-Addressed Flat Panel Display,xe2x80x9d issued Aug. 15, 1989, to Charles A. Spindt et al., incorporated herein by reference. This arrangement includes a matrix array of individually addressable light generating means of the cathodoluminescent type having electron emitting cathodes combined with an anode which is a luminescing means of the CRT type which reacts to electron bombardment by emitting visible light. Each cathode is itself an array of thin film field emission cathodes on a backing plate, and the luminescing means is provided as a phosphor coating on a transparent face plate which is closely spaced to the cathodes.
The emitter backing plate disclosed in the Spindt et al. (""799) patent includes a large number of parallel vertical conductive cathode electrodes which extend across the backing plate and are individually addressable. A multiplicity of spaced-apart electron emitting tips project upwardly from each vertical cathode electrode on the backing plate and extend perpendicularly away from the backing plate. An electrically conductive gate electrode arrangement is positioned adjacent to the tips to generate and control the electron emission. The gate electrode arrangement comprises a large number of individually addressable, parallel horizontal electrode stripes which extend along the backing plate orthogonal to the cathode electrodes, and which include apertures through which emitted electrons may pass. Each gate electrode is common to a full row of pixels extending across the front face of the backing plate and is electrically isolated from the arrangement of cathode electrodes. The emitter back plate and the anode face plate are parallel and spaced apart.
The anode is a thin film of an electrically conductive transparent material, such as indium tin oxide, which covers the interior surface of the face plate. Deposited onto this metal layer is a luminescent material, such as phosphor, that emits light when bombarded by electrons.
The array of emitting tips are activated by addressing the orthogonally related cathode gate electrodes in a generally conventional matrix-addressing scheme. The appropriate cathode electrodes of the display along a selected stripe, such as along one column, are energized while the remaining cathode electrodes are not energized. Gate electrodes of a selected stripe orthogonal to the selected cathode electrode are also energized while the remaining gate electrodes are not energized, with the result that the emitting tips of a pixel at the intersection of the selected cathode and gate electrodes will be simultaneously energized, emitting electrons so as to provide the desired pixel display.
The Spindt et al. patent teaches that it is preferable that an entire row of pixels be simultaneously energized, rather than energization of individual pixels. According to this scheme, sequential lines are energized to provide a display frame, as opposed to sequential energization of individual pixels in a raster scan manner.
The Clerc (""820) patent discloses a trichromatic FED flat panel display having a first substrate comprising the cathode and gate electrodes, and having a second substrate facing the first, including regularly spaced, parallel conductive stripes comprising the anode electrode. These stripes are alternately covered by a first material luminescing in the red, a second material luminescing in the green, and a third material luminescing in the blue, the conductive stripes covered by the same luminescent material being electrically interconnected.
Today, a conventional FED is manufactured by combining the teachings of many practitioners, including the teachings of the Spindt et al. (""799) and Clerc (""820) patents. Referring initially to FIG. 1, there is shown, in cross-sectional view, a portion of an illustrative FED in which the present invention may be incorporated. In this embodiment, the FED comprises an anode plate 1 having an electroluminescent phosphor coating 3 facing an emitter plate 2, the phosphor coating 3 being observed from the side opposite to its excitation.
More specifically, the FED of FIG. 1 comprises a cathodoluminescent anode plate 1 and an electron emitter (or cathode) plate 2. A cathode portion of emitter plate 2 includes conductors 9 formed on an insulating substrate 10, an electrically resistive layer 8 which is formed on substrate 10 and overlaying the conductors 9, and a multiplicity of electrically conductive microtips 5 formed on the resistive layer 8. In this example, the conductors 9 comprise a mesh structure, and microtip emitters 5 are configured as a matrix within the mesh spacings. Microtips 5 take the shape of cones which are formed within apertures through conductive layer 6 and insulating layer 7.
A gate electrode comprises the layer of the electrically conductive material 6 which is deposited on the insulating layer 7. The thicknesses of gate electrode layer 6 and insulating layer 7 are chosen in such a way that the apex of each microtip 5 is substantially level with the electrically conductive gate electrode layer 6. Conductive layer 6 may be in the form of a continuous layer across the surface of substrate 10; alternatively, it may comprise conductive bands across the surface of substrate 10.
Anode plate 1 comprises a transparent, electrically conductive film 12 deposited on a transparent planar support 13, such as glass, which is positioned facing gate electrode 6 and parallel thereto, the conductive film 12 being deposited on the surface of the glass support 13 directly facing gate electrode 6. Conductive film 12 may be in the form of a continuous layer across the surface of the glass support 13; alternatively, it may be in the form of electrically isolated stripes comprising three series of parallel conductive bands across the surface of the glass support 13, as shown in FIG. 1 and as taught in U.S. Pat. No. 5,225,820, to Clerc. By way of example, a suitable material for use as conductive film 12 may be indium-tin-oxide (ITO), which is optically transparent and electrically conductive. Anode plate 1 also comprises a cathodoluminescent phosphor coating 3, deposited over conductive film 12 so as to be directly facing and immediately adjacent gate electrode 6. In the Clerc patent, the conductive bands of each series are covered with a particulate phosphor coating which luminesces in one of the three primary colors, red, blue and green 3R, 3B, 3G.
Selected groupings of microtip emitters 5 of the above-described structure are energized by applying a negative potential to cathode electrode 9 relative to the gate electrode 6, via voltage supply 19, thereby inducing an electric field which draws electrons from the apexes of microtips 5. The potential between cathode electrode 9 and gate electrode 6 is approximately 70-100 volts. The freed electrons are accelerated toward the anode plate 1 which is positively biased by the application of a substantially larger positive voltage from voltage supply 11 coupled between the cathode electrode 9 and conductive film 12 functioning as the anode electrode. The potential between cathode electrode 9 and anode electrode 12 is approximately 300-800 volts. Energy from the electrons attracted to the anode conductive film 12 is transferred to particles of the phosphor coating 3, resulting in luminescence. The electron charge is transferred from phosphor coating 3 to conductive film 12, completing the electrical circuit to voltage supply 11. The image created by the phosphor stripes is observed from the anode side which is opposite to the phosphor excitation, as indicated in FIG. 1.
It is to be noted and understood that true scaling information is not intended to be conveyed by the relative sizes and positioning of the elements of anode plate 1 and the elements of emitter plate 2 as depicted in FIG. 1. For example, in a typical FED shown in FIG. 1 there are approximately one hundred arrays 4, of microtips and there are three color stripes 3R, 3R, 3G per display pixel.
The process of producing each frame of a display using a typical trichromatic field emission display includes a) applying an accelerating potential to the red anode stripes while sequentially addressing the gate electrodes (row lines) with the corresponding red video data for that frame applied to the cathode electrodes (column lines); b) switching the accelerating potential to the green anode stripes while sequentially addressing the rows lines for a second time with the corresponding green video data for that frame applied to the column lines; and c) switching the accelerating potential to the blue anode stripes while sequentially addressing the row lines for a third time with the corresponding blue video data for that frame applied to the column lines. This process is repeated for each display frame.
FIG. 2 is a block diagram of a portion of a field emission display electronics system as disclosed in U.S. patent application Ser. No. 08/332,182, xe2x80x9cField Emission Device Automatic Anode Voltage Adjuster,xe2x80x9d filed Oct. 31, 1994(Texas Instruments, Inc. Docket No. TI-19620), incorporated herein by reference. As indicated in FIG. 2, anode plate 1 is physically located over emitter plate 2; however, anode plate 1 and emitter plate 2 are separated in the drawing in order to better show the elements comprising plates 1 and 2 of the FED display. Elements which are part of the system but which are unimportant to the understanding of the field emission display are not shown.
Anode power supply 20 provides a high voltage source to an anode switching control 22, typically between 300 and 800 volts. The anode voltage switching control 22, responsive to commands issued from data formatting and timing controller 24, provides voltages simultaneously (if the image is in monochrome) or sequentially (if the image is in color) to the three anode stripes 3R, 3G and 3B, each of the anode stripe voltages being set to a level in accordance with the brightness characteristics of the corresponding luminescent material.
The cathode electrodes 9 (column lines) of matrix-addressable cathode emitter plate 2 are individually coupled to column drivers 26. The column drivers 26 receive video data from a host device, which has been formatted by the data formatter and timing controller 24 into separate red, green, and blue display frames from an original mixed signal. In this example, the data formatter and timing controller 24 may process the video data according to the VGA standard, and may typically output data to the column drivers 26 for output on 640 parallel lines, to thereby provide one color component of a single row of the display. The data from the data formatter and timing controller 24 is latched into the column drivers 26 upon each occurrence of a clock signal received at the CLK input terminal.
The gate electrodes 6 (row lines) of matrix-addressable cathode plate 2 are individually coupled to row drivers 28. The row drivers 28 receive enable signals from row address counter/decoder 30. The device 30 includes a counter which is responsive to each occurrence of a clock signal received at a CLK input terminal, and a decoder which applies an enabling signal sequentially to each of the row drivers 28. In this example, the counter of the device 30 may count to 480, the decoder portion of the device 30 applying enabling signals sequentially to each of the row drivers-28, to thereby address each of the 480 output lines.
The data formatter and timing controller 24 also receives a synchronization input signal from the host. The sync input contains the clock, horizontal sync, and vertical sync information.
The data formatter and timing controller 24 is coupled to frame memory 32. The memory 32 holds the luminance information corresponding to two red pixels, two green pixels and two blue pixels. For illustration purposes, memory 32 comprises 307,200 words of 12-bit length, which is the capacity necessary to store two full frames of six bits of luminance information for each pixel of a 640-column by 480-row display system.
In accordance with a field sequential mode of operation, an entire frame of red luminance information is first clocked out of the memory 32. After an entire frame of red luminance information has been transferred from the memory 32 a similar process is repeated for an entire frame of green luminance information, and thereafter for an entire frame of blue luminance information. This entire process is repeated continuously while an image is displayed by the FED. The eye is a slow detector compared with the frame time and the perception of the full color is due to an averaging effect over several image frames. Therefore, the color sensation perceived by a person viewing the FED is due to a reconstitution of the colored spectrum by the viewer""s eye.
As indicated in FIG. 2, all red stripes 3R are electrically coupled together. All green stripes 3G and all blue stripes 3B are also electrically coupled to each other. The prior art structure used to facilitate the electrical interconnection of the color anode stripes 3R, 3G, and 3B, is shown in FIGS. 3 and 4. FIG. 3 shows the manner in which the conductive film 34 of the anode stripes 34 are interconnected in the prior art. The conductive films 34 are substantially similar to the conductive film 12 of FIG. 1. Conductive film 34R is covered with a phosphor coating luminescing in red, conductive film 34B is covered with a phosphor coating luminescing in blue, and conductive film 34G is covered with a phosphor coating luminescing in green.
The conductive films 34R are electrically interconnected by a first conductive band 36. The conductive films 34G are electrically interconnected by a second conductive band 38. The conductive films 34B are electrically interconnected by a anisotropic conductive ribbon 40 described more fully below. The first and second conductive bands 36, 38 are formed on the anode plate 1 during the at the same time the conductive films 34 are formed. The conductive bands 36, 38 and the conductive films 34 are also coplanar and both are comprised of the same conductive material, illustratively indium-tin-oxide (ITO).
The conductive films 34R which are connected to band 36 are interdigitated with the conductive films 34G which are connected to band 38 and the conductive films 34B, which are connected to band 40. The anisotropic conductive ribbon 40 is deposited perpendicular to the conductive films 34.
FIG. 4 shows a section of the anode plate 1 along the anisotropic conductive ribbon 40. The anisotropic ribbon 40 is essentially formed by a conductive strip 40xe2x80x3 and a film 40xe2x80x2. The film 40xe2x80x2 comprises carbide balls 42 distributed in an insulating binder forming the film 40xe2x80x2, so as not to conduct electricity. As can be seen from FIG. 4, the conductive strip 40xe2x80x3 crushes the film 40xe2x80x2 at the conductive films 34B. The density of the balls 42 is such that at the crushed points the balls 42 are in contact. The ribbon 40 becomes conductive at these points. The conductive films 34B are electrically connected to the conductive ribbon 40xe2x80x3, but the non-crushed locations of film 40xe2x80x2 are insulating.
There are numerous disadvantages to the prior art structure used to interconnect the red, green, and blue anode stripes. First, the use of the externally attached anisotropic ribbon 40 to connect the conductive films 34B, creates a significant FED system reliability problem. If the ribbon 40 isn""t assembled to anode plate 1 properly then the conductive films 34 of two or three colors will be shorted together. Furthermore, the ribbon 40 can become disconnected from the conductive films 34B causing lines to appear in the display image at the places where the conductive films 34B, are not electrically connected to the ribbon 40.
What is needed is an alternative structure to the external conductive ribbon, and a multilevel metal structure which has a lowered probability of interlevel oxide failures. More ideally, what is needed is a bus structure which has a reduced failure rate.
A field emission display apparatus is comprised of an emitter plate comprising a plurality of column conductors intersecting a plurality of row conductors, and electron emitters at the intersection of each of the row and column conductors. An anode plate is adjacent to the emitter plate, the anode plate comprising conductive stripes which are alternately covered by materials luminescing in the three primary colors. The conductive stripes covered by the same luminescent material are electrically interconnected to form comb-like structures corresponding to each of the colors. The anode plate contains an active region and the buses have a non-uniform width.
The use of the step-wise width incrementing bus structure, as disclosed herein, has numerous advantages including the reduction in failure rate of the insulator between the bus and overlying or underlying conductors. First, the reduction in failure rate realized by the step-wise bus structure of the present invention is supplemental to any other techniques used to reduce the failure rate of DLM designs such as increasing the metal thickness to reduce metal width. In addition, implementation of the step-wise bus structure is cost-free; no extra design or manufacturing costs are incurred by implementing the present invention. Furthermore, the implementation of the present invention improves reliability by approximately 96.7%, resulting in significant cost savings.